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? ? YTD428 application manual catalog no.: lsi-6td428a3 2 ? 2005 .1 ? YTD428 application manual idsu isdn dsu for terminal equipment ?

contents - 1 - contents 1. introduction ..................................................................................... 2 1.1 features ................................................................................................................... ............. 3 2. block diagram .................................................................................. 4 2.1 internal block diagram ..................................................................................................... ..... 4 2.2 dsu configuration example ................................................................................................. 5 3. pin descriptions .............................................................................. 7 3.1 pin assignments ............................................................................................................ ........ 7 3.2 pin functions .............................................................................................................. .......... 8 4. details of functions.................................................................... 13 4.1 u reference point section .................................................................................................. 13 4.2 circuit termination / line termination section .................................................................... 13 4.3 interface switch section ................................................................................................... ... 14 4.4 t reference interface section ............................................................................................ 15 5. electrical characteristics ..................................................... 16 5.1 absolute maximum ratings ................................................................................................. 16 5.2 recommended operating conditions ................................................................................. 16 5.3 dc characteristics ......................................................................................................... ..... 17 5.4 ac characteristics ......................................................................................................... ...... 18 6. pin descriptions ............................................................................ 22 reference circuit ............................................................................ 23
- 2 - introduction 1. introduction YTD428 is a lsi which provides the isdn subscriber interface (two-wire time compression multiplexing operation) and the nt side of the isdn basic rate user-network interface function (digital four-wire time-division full-duplex operation). it is capable of providing the electric characteristics conforming to ttc standard jt-i430 and jt-g961. YTD428 incorporates the circuit termination and line termination functions on a single chip allowing the user to easily configure a dsu (digital service unit) that consumes small amount of power at a minimal cost. in addition, a ttl interface is provided at the t reference point (layer 1 level). this feature is especially effective when combined with yamaha's isdn lsi for s/t reference point interface, ytd423 or ytd418. it allows considerable cost reduction on parts around the pulse transformer when constructing a device with a built-in dsu. the driver/receiver section of the t reference point interface can be separated from the dsu section and be used independently. the user can enable or disable this feature as necessary.
introduction - 3 - 1.1 features circuit termination section line termination section t reference point interface section others
- 4 - block diagram 2. block diagram 2.1 internal block diagram adc ct block interface switch section ttl i/f u ref. pt. driver control lt block s/t ref. pt. lsi ytd418 or ytd423 t ref. pt. i/f section u ref. pt. i/f section YTD428 ct/lt section t ref. pt. receiver t ref. pt. driver peak hold variable amplifier t ref. pt. side u ref. pt. side ct : circuit termination lt : line termination
block diagram - 5 - 2.2 dsu configuration example YTD428 incorporates the circuit termination, line termination, t reference point interface and u reference point interface functions on a single chip allowing the user to easily configure a dsu that consumes small amount of power at a minimal cost. the user can select from the two types of configurations. one is the general configuration in which a transformer is used at the t reference point interface. the other is a configuration in which a ttl interface is used to directly connect to the t reference point lsi. configuration example of a general dsu various functions are incorporated on a single chip allowing the user to create a low power-consuming product at a low cost. ym7405 or ytd410 for s/t ref. pt. included driver/receiver for s/t ref. pt. YTD428 dsu l1 ta / tb ra / rb l2 layer 3 info. bch data call control circuit u ref. pt. driver t ref. pt. u ref. pt. side
- 6 - block diagram YTD428 dsu section call control circuit u ref. pt. driver layer 3 information (bch data) i.430 ttl i/f (no transformer is requied) ytd418 or ytd423 i/f switch ct and lt u ref. pt. i/f t ref. pt. i/f l1 ta / tb ra / rb l2 t ref. pt. side (to terminal) u ref. pt. side YTD428 dsu section call control circuit u ref. pt. driver ytd418 or ytd423 i/f switch ct and lt u ref. pt. i/f t ref. pt. i/f ttl i/f (no transformer is required) l1 ta / tb ra / rb l2 t ref. pt. side (dsu) u ref. pt. side layer 3 information (bch data) configuration example of a device with a built-in dsu that uses an i.430 ttl interface at the t ref. pt. when using YTD428 with yamaha's s/t reference point interface lsi to create a device with a built-in dsu, they can be connected directly through the i.430 ttl interface. this results in a reduction of pulse transformer parts. example of using t reference point driver / receiver section independently by setting the interface switch, the drive / receiver of the t reference point interface section can be separated from the circuit termination (ct) and line termination (lt) section and be used independently. the user can enable or disable this feature as necessary.
pin descriptions - 7 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 66 67 68 69 70 71 72 73 74 75 65 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 YTD428-s 100pin sqfp tsmpsel powmon clk400 test15 test14 test13 test12 test11 test10 test9 exid dv ss dv dd clk200 clk4k clk256k dv ss ltd htd lrd hrd rdp odsel tdp multi rev ntsel dv dd clk1536 dv dd test7 dv ss test6 test5 test4 dv dd local test3 test2 test1 lpsel test0 reset dv ss loop2a lpsw test16 clk192k test8 tsmpaut test25 test26 test27 test28 dv ss dv ss udm0 udm1 udp0 udp1 test23 dv dd test24 av ss 1 test17 test19 test20 test21 test22 clksel test18 vrb vrt av dd 1 atei av ss 2 av ss 2 lict li1 av dd 1 rxs sgb sgbp sxa sga sgr av ss 1 rxu1 rxu2 ruc av ss 1 cx2 li2 cx1 lo1 av dd 2 lo2 rx av dd 2 ateo 3. pin descriptions 3.1 pin assignments
- 8 - pin descriptions 3.2 pin functions common section . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 6 9 , 3 1 , 3v a s s 1d n g) . t p . f e r u ( 1 d n u o r g g o l a n a 5 2 , 4 1v a s s 2d n g) . t p . f e r t ( 2 d n u o r g g o l a n a , 8 5 , 3 4 , 6 2 5 9 , 3 8 , 5 6 v d s s d n gd n u o r g l a t i g i d 9 9 , 8v a d d 1r w p) . t p . f e r u ( 1 y l p p u s r e w o p g o l a n a % 5 v 5 + 2 2 , 9 1v a d d 2r w p) . t p . f e r t ( 2 y l p p u s r e w o p g o l a n a % 5 v 5 + 0 6 , 0 5 , 1 3 8 8 , 4 7 v d d d r w py l p p u s r e w o p l a t i g i d % 5 v 5 + 9 56 3 5 1 k l cn i) s s e l r o m p p 0 5 z h m 6 3 . 5 1 ( k c o l c m e t s y s 1 4n o m w o pn i e d i s . t p . f e r t e h t n o t n e m p i u q e e h t f o r o t i n o m y l p p u s r e w o p f f o y l p p u s r e w o p : " h " n o y l p p u s r e w o p : " l " 2 4t e s e rn i t e s e r e r a w d r e a h e t a r e p o o t n o i t a l l i c s o k c o l c e h t r e t f a e r o m r o s m 1 r o f e s l u p t e s e r e h t y l p p a s i n o i t a r e p o e h t , s m 1 n a h t s s e l s i e s l u p e h t f i . t e s e r e r a w d r a h . e l b a t c i d e r p n u . t e m e r a s n o i t i d n o c g n i w o l l o f l l a n e h w d e r i u q e r s i t e s e r e r a w d r a h r e w o p l a c o l y b d e t a r e p o . 1 " h " = l e s p l . 2 . e v i t i s o p s i y t i r a l o p . t p . f e r u . 3 note connect input pins that are not normally used to the power supply pin or ground pin. in the same fashion, do not leave pins with pull-up resistor open. connect them to the power supply pin or ground pin.
pin descriptions - 9 - mode setting section . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 3 3p d tn i g n i t t e s y t i r a l o p e s l u p d t l , d t h y t i r a l o p e v i t i s o p : " h " y t i r a l o p e v i t a g e n : " l " p u - l l u p h t i w r o t s i s e r 4 3p d rn i g n i t t e s y t i r a l o p e s l u p d r l , d r h y t i r a l o p e v i t i s o p : " h " y t i r a l o p e v i t a g e n : " l " p u - l l u p h t i w r o t s i s e r 5 3l e s d on i g n i t t e s l a n g i s t i m s n a r t . t p . f e r t t u p t u o l a m r o n s n i p d r l , d r h : " h " n i a r d n e p o s n i p d r l , d r h : " l " p u - l l u p h t i w r o t s i s e r 6 3l e s p m s tn i g n i t t e s g n i m i t g n i l p m a s a t a d e v i e c e r . t p . f e r t ) s u b e v i s s a p t r o h s ( g n i m i t d e x i f : " h " , ) " l " = t u a p m s t ( " c i t a m o t u a " o t t e s s i e d o m g n i l p m a s a t a d . t p . f e r t n e h w . " h " o t n i p s i h t t e s ) s u b e v i s s a p d e d n e t x e , n o i t c e n n o c t n i o p - o t - t n i o p ( g n i m i t e v i t p a d a : " l " p u - l l u p h t i w r o t s i s e r 7 3t u a p m s tn i g n i t t e s e d o m g n i l p m a s a t a d . t p . f e r t ) d i l a v s i e t a t s n i p l e s p m s t ( g n i t t e s l a u n a m : " h " ) " h " o t n i p l e s p m s t t e s ( g n i t t e s c i t a m o t u a : " l " p u - l l u p h t i w r o t s i s e r 8 3i t l u mn i g n i t t e s t r o p p u s e m a r f i t l u m . t p . f e r t e m a r f i t l u m t r o p p u s : " h " e m a r f i t l u m t r o p p u s t o n o d : " l " p u - l l u p h t i w r o t s i s e r 9 3l e s t nn i g n i t t e s e d o m . t p . f e r t e d o m t n : " h " ) k c o l b u s d f o y l t n e d n e p e d n i s e t a r e p o k c o l b f / i . t p . f e r t ( e d o m e t : " l " p u - l l u p h t i w r o t s i s e r 4 4l a c o ln i g n i t t e s e d o m g n i d e e f r e w o p e d o m g n i d e e f r e w o p m o t n a h p : " h " e d o m g n i d d e f r e w o p l a c o l : " l " p u - l l u p h t i w r o t s i s e r 5 4l e s p ln i g n i t t e s l a n g i s w s p l a 2 k c a b p o o l d e d n e t x e y l n o l l a c : " h " a 2 k c a b p o o l d e d n e t x e y b l l a c , l l a c l a m r o n : " l " ) e d o m g n i d e e f r e w o p l a c o l t a l a n g i s l o r t n o c p o o l ( p u - l l u p h t i w r o t s i s e r 6 6d i x en i g n i t t e s k c a b p o o l ) 2 k c a b p o o l d e d n e t x e o t d n o p s e r r o c ( " 1 " = 1 d i t i m s n a r t : " h " ) " 1 " = p a t a s e t a r e p o a 2 k c a b p o o l ( " 0 " = 1 d i t i m s n a r t : " l " p u - l l u p h t i w r o t s i s e r 2 8l e s k l cn i g n i t t e s t u p t u o k c o l c k c o l c t u p t u o t o n o d : " h " k c o l c t u p t u o : " l " p u - l l u p h t i w r o t s i s e r note 1 when not using ttl interface, set htd, ltd pins as bellow. when tdp = h, set htd, ltd = l when tdp = l, set htd, ltd = h note 2 when using the YTD428 on a terminal with built-in dsu, it is recommended that fixed timing be selected for the sample timing of t reference point receive data (tsmpsel=h and tsmpaut=h). this is because the bus distribution form becomes a short passive bus in this case. note 3 when using ntsel, external terminating resistor setting is required. when ntsel = h, terminating resistor is required. when ntsel = l, remove terminating resistor as necessary. note 4 set local = l when lpsel = l or clksel = l.
- 10 - pin descriptions t reference point section note when not using ttl interface, set htd, ltd pins as bellow. when tdp = h, set htd, ltd = l when tdp = l, set htd, ltd = h . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 5 11 i ln it u p n i e n i l t / s 6 1t c i lt u ot u p t u o e c r u o s e c n e r e f e r e n i l t / s 7 12 x c- r o t s i s e r d n a r o t i c a p a c l a n r e t x e g n i t c e n n o c m 1 d n a r o t i c a p a c f 1 . 0 ? ? . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 7 2d r ht u o ) + ( a t a d t i m s n a r t u s d : " h " = l e s t n ) + ( a t a d e v i e c e r e t : " l " = l e s t n 8 2d r lt u o ( a t a d t i m s n a r t u s d : " h " = l e s t n- -) ( a t a d e v i e c e r e t : " l " = l e s t n- -) 9 2d t hn i ) + ( a t a d e v i e c e r u s d : " h " = l e s t n ) + ( a t a d t i m s n a r t e t : " l " = l e s t n 0 3d t ln i ( a t a d e v i e c e r u s d : " h " = l e s t n- -) ( a t a d t i m s n a r t e t : " l " = l e s t n- -) note 1 when not using t ref. pt. analog interface, set these pins as bellow. the li1, li2 and lict pins are to be connected each other (short). 0.1 note 2 about how to connect external capacitor and resistor, refer to reference circuit .
pin descriptions - 11 - u reference point section . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 21 u x rn i1 t u p n i l a n g i s e v i e c e r 4r g st u ot u p t u o e c n e r e f e r l a n g i s g o l a n a 52 u x rn i2 t u p n i l a n g i s e v i e c e r 6c u r- v a e h t d n a n i p c u r e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c f 1 . 0 s s . n i p 1 7a g s- ) % 0 1 ( f 7 4 0 0 . 0e h t d n a n i p a g s e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c r g s. n i p 9s x r- f 2 2 0 0 . 0) % 0 1 (e h t d n a n i p s x r e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c . n i p r g s 0 1b g s- f 5 1 0 . 0) % 0 1 (e h t d n a n i p b g s e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c . n i p r g s 1 1p b g s- f 5 1 . 0) % 0 1 (e h t d n a n i p p b g s e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c . n i p r g s 2 1a x s- . d e t c e n n o c n u t f e l e b t s u m n i p s i h t 7 9b r vt u o ) e g a t l o v w o l ( y l p p u s r e w o p e c n e r e f e r c d a v a e h t d n a n i p b r v e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c f 1 . 0 s s . n i p 1 8 9t r vt u o ) e g a t l o v h g i h ( y l p p u s r e w o p e c n e r e f e r c d a v a e h t d n a n i p t r v e h t s s o r c a d e t c e n n o c e b o t s i r o t i c a p a c f 1 . 0 s s . n i p 1 . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 0 4v e rn i y t i r a l o p . t p . f e r u . " h " o t n i p s i h t t e s , " h " = l e s p l n e h w . w o l l e b s a n i p s i h t t e s , " l " = l e s p l n e h w y t i r a l o p e v i t i s o p : " l " y t i t a l o p e s r e v e r : " h " 5 5a 2 p o o lt u o n o i t a r e p o l a m r o n : " l " 2 k a b p o o l g n i t a c i d n i : " h " 6 5w s p lt u o l a n g i s l o r t n o c l l a c n o i t a r e p o l a m r o n : " l " t s e u q e r e t a i t i n i l l a c : " h " . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 4 80 m d ut u ol a n g i s g n i v i r d e s l u p e v i t a g e n 5 81 m d ut u ol a n g i s g n i v i r d e s l u p e v i t a g e n 6 80 p d ut u ol a n g i s g n i v i r d e s l u p e v i t i s o p 7 81 p d ut u ol a n g i s g n i v i r d e s l u p e v i t i s o p
- 12 - pin descriptions clock output pins test pins these are for lsi examinations, and not used in normal operation. be sure that each pin is set as bellow. . o n n i pe m a n n i po / in o i t c n u fs k r a m e r 2 3k 2 9 1 k l ct u o ) " l " o t d e x i f y l l a u s u ( k c o l c z h k 2 9 1 . " l " = l a c o l d n a " l " = l e s k l c n e h w k c o l c t u p t u o 2 , 1 e t o n 1 6k 4 k l ct u o ) " l " o t d e x i f y l l a u s u ( k c o l c z h k 4 . " l " = l a c o l d n a " l " = l e s k l c n e h w k c o l c t u p t u o 2 , 1 e t o n 2 6k 6 5 2 k l ct u o ) " l " o t d e x i f y l l a u s u ( k c o l c z h k 6 5 2 . " l " = l a c o l d n a " l " = l e s k l c n e h w k c o l c t u p t u o 1 e t o n 3 60 0 2 k l ct u o ) " l " o t d e x i f y l l a u s u ( k c o l c z h 0 0 2 . " l " = l e s k l c n e h w k c o l c t u p t u o 2 , 1 e t o n 4 60 0 4 k l ct u o ) " l " o t d e x i f y l l a u s u ( k c o l c z h 0 0 4 . " l " = l e s k l c n e h w k c o l c t u p t u o 2 , 1 e t o n . o n n i pe m a n n i po / in o i t c n u fs k r a m e r , 9 4 , 8 4 , 6 4 51~5 , 4 , 7 6 , 7 5 1 8 , 0 8 , 0 t s e t , 9 ~ 2 2 2 , 1 2 n i n i p t s e t . " h " o t d e x i f y l l a u s u p u - l l u p h t i w r o t s i s e r 3 9 ~ 1 9 , 9 8 t s e t 7 2 ~ 5 2 , 3 2 n i n i p t s e t . " l " o t d e x i f y l l a u s u 4 98 2 t s e tn i n i p t s e t . " h " o t d e x i f y l l a u s u 8 7 ~ 5 7 , 7 4 , 1 t s e t 9 1 ~ 6 1 o / i n i p t s e t . " h " o t p u l l u p y l l a u s u p u - l l u p h t i w r o t s i s e r 0 9 , 9 6 , 8 6 , 0 1 t s e t 4 2 , 1 1 o / i n i p t s e t . " h " o t p u l l u p y l l a u s u 3 7 ~ 0 7 t s e t 5 1 ~ 2 1 o / i n i p t s e t . " l " o t d e x i f y l l a u s u 9 70 2 t s e tt u o n i p t s e t . d e t c e n n o c n u t f e l e b t s u m n i p s i h t 0 0 1i e t an i n i p t s e t . " l " o t d e x i f y l l a u s u 1o e t ao / i n i p t s e t . " h " o t p u d e l l u p y l l a u s u note 1 outputs ??when the YTD428 is set to not output the clock. in addition, if the YTD428 is not synchronized to the network, the frequency of the output clock is not guaranteed. note 2 clock is output when rev = ?.
details of functions - 13 - 4. details of functions 4.1 u reference point section variable amplifier this block amplifies the receive signal amplitude to the maximum dynamic range. adc this block makes an a/d conversion of the received signal and transfers it to the line termination block. peak hold this block is performed during the initial training so that the gain of the variable amplifier block is set to make best communication condition. 4.2 circuit termination / line termination section circuit termination block the following functions provide the necessary functions for ttc standard jt-g961 (tcm operation) and the nt function described in ttc standard jt-i430. YTD428 supports loopback 2 and loopback c for testing and maintenance. these loopback tests are under local switch control. line termination block the line termination provides the f equalization which compensates the dll (digital local line) loss and the amplitude distortion, and the bt equalization which compensates the waveform distortion caused by the bridged tap.
- 14 - details of functions YTD428 dsu section call control circuit u ref. pt. driver ytd418 or ytd423 i/f switch ct and lt u ref. pt. i/f t ref. pt. i/f ttl i/f (no transformer is required) l1 ta / tb ra / rb l2 t ref. pt. side (dsu) u ref. pt. side layer 3 information (bch data) figure 4.1 image of using t ref. pt. i/f drive/receiver independently in case of using ntsel = "l" (te mode), the signals of ta/tb and ra/rb should be reversed by switches or other devices. because s/t bus signals that are connected to ta, tb, ra and rb pin are different between using YTD428 as dsu (ntsel = "h") and s/t terminal (ntsel = "l"). generally speaking, the terminal resistors are only mounted on the nearest terminal from dsu and other terminals that are connected with the same bus don't require the terminal resistors. therefore, it is useful that switches which can control on/off of the terminal resistors are provided on the equipment. 4.3 interface switch section normally, this section connects t i/f section with ct/lt section to provide dsu function (ntsel = h ). by setting this section, the driver/receiver function of the t i/f section can be separated from the ct/lt section and be used independently (ntsel = l ). for example, it is useful under such a situation that there are some terminals which have dsu function on the same s/t line.
details of functions - 15 - - 0 + 0 192khz i.430 receive signal (ra/rb) hrd pin (ttl level) lrd pin (ttl level) (ami) (nrz) (nrz) - 0 + 0 192khz i.430 transmit signal (ta/tb) htd pin (ttl level) ltd pin (ttl level) (ami) (nrz) (nrz) 4.4 t reference interface section reference power supply block this block provides the electric power to supply for the receiver block and the driver block. receiver block the receiver block receives signal from the s/t bus through the external pulse transformer and converts it to the logic level signal. the voltage threshold level for he receiver is properly adapted automatically according to the receiving signal level. driver block the driver block drives the 2:1 turn ratio transformer according to the logic level transmitting signal. figure 4.2 receive signal logic (rdp = h , ntsel = l ) figure 4.3 transmit signal logic (tdp = h , ntsel = l )
- 16 - electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings r e t e m a r a pl o b m y s. n i mx a ms t i n u e g a t l o v y l p p u sv d d v s s 3 . 0 -v s s 0 . 7 +v e g a t l o v t u p n iv i v s s 3 . 0 -v d d 3 . 0 +v e r u t a r e p m e t e g a r o t st g t s 0 5 -5 2 1 +c ? r e t e m a r a pl o b m y se g n a r e g a t l o v y l p p u sv d d % 5 v 0 . 5 e r u t a r e p m e t g n i t a r e p ot p o c ? 0 7 + ~ 0 2 - 5.2 recommended operating conditions
electrical characteristics - 17 - r e t e m a r a pl o b m y sn o i t i d n o c. n i m. p y t. x a ms t i n u ) l t t ( e g a t l o v t u p n i l e v e l h g i h v h i ( 1 e t o n )2 . 2v v h i ( 2 e t o n )0 . 3v ) l t t ( e g a t l o v t u p n i l e v e l w o l v l i ( 1 e t o n )8 . 0v v l i ( 2 e t o n )8 . 0v ) s o m c ( e g a t l o v t u p n i l e v e l h g i hv h i ( 3 e t o n )5 . 3v ) s m o c ( e g a t l o v t u p n i l e v e l w o lv l i ( 3 e t o n )0 . 1v ) l t t ( e g a t l o v t u p t u o l e v e l h g i hv h o ( 4 e t o n )v d d d 0 . 1 -v ( 5 e t o n )v d d d 0 . 1 -v ) l t t ( e g a t l o v t u p t u o l e v e l w o lv l o ( 4 e t o n )v d s s 4 . 0 +v ( 5 e t o n )v d s s 4 . 0 +v ) d - n e p o ( e g a t l o v t u p t u o l e v e l w o lv l o ( 6 e t o n )v d s s 4 . 0 +v t n e r r u c k a e li l 0 1 -0 1a t n e r r u c k a e l n o i t i d n o c e l d ii z l 0 1 -0 1a t n e r r u c y l p p u s r e w o pi d d ( 7 e t o n )6 3a m r e t e m a r a pl o b m y sn o i t i d n o c. n i m. p y t. x a ms t i n u e l b a w o l l a t u p t u o g o l a n a e c n a d e p m i d a o l z o 1 e t o n 0 3k r e f f u b e v i e c e r g o l a n a e c n a d e p m i t u p n i z 1 i 2 e t o n 0 1m e c n e r e f e r l a n g i s g o l a n a e g a t l o v v g s 3 e t o n 5 4 . 20 5 . 25 5 . 2v c d a t r v s a i b - f l e sv t r 4 e t o n v a 7 . 0 d d 1 . 0 -v a 7 . 0 d d v a 7 . 0 d d 1 . 0 +v b r v s a i b - f l e sv b r 5 e t o n v a 3 . 0 d d 1 . 0 -v a 3 . 0 d d v a 3 . 0 d d 1 . 0 +v 5.3 dc characteristics (dv dd = av dd = 5 .0v, dv ss = av ss = 0.0 v, operating temperature: t op = 25 c) note 1 with respect to sgr, sxa pins. note 2 with respect to rxu1 and rxu2 pins. note 3 set sgr pin to open. note 4 with respect to vrt pin. note 5 with respect to vrb pin. (dv dd = av dd = 5.0 5% v, t op = -20 ~ 70 c) note 1 with respect to the digital pins other than reset, powdet, clk1536 and test23 ~ 28 pins note 2 with respect to reset, powdet pins note 3 with respect to clk1536, test23 ~ 28 pins note 4 with respect to the pin other than hrd, lrd pins test condition: output current "h" level (i oh ) = -0.2 ma, output current "l" level (i ol ) = 1.2 ma note 5 with respect to hrd, lrd pins (when odsel = "h"), test condition: i oh = -0.2 ma, i ol = 1.2 ma note 6 with respect to hrd, lrd pins (when odsel = "l"), test condition: i ol = 1.2 ma note 7 when using t ref. pt. analog interface
- 18 - electrical characteristics r e t e m a r a pl o b m y sn o i t i d n o c. n i m. p y t. x a ms t i n u h t d i w e s l u p t i m s n a r tt w p t 0 0 . 58 0 2 . 50 4 . 5s h t d i w e s l u p e v i e c e rt w p r 8 0 2 . 5s e m i t e s i rt r p 0 6 2s n e m i t l l a ft f p 0 3s n n e e w t e b e c n e r e i f f i d e s a h p s l a n g i s x r d n a x t t d r t 1 e t o n 0 . 0 10 . 4 1s t d r t 2 e t o n 0 . 0 10 . 2 4s n e e w t e b e c n e r e f f i d e s a h p s l a n g i s x r t h p 2 e t o n , 3 e t o n 0 . 2s 5.4 ac characteristics t reference point receive characteristic (nt mode) (v dd = 5.0 5% v , t op = -20 ~ 70 c, load capacity: c l = 50 pf) note 1 with respect to using the fixed timing note 2 with respect to using the adaptive timing note 3 this value shows the difference between two terminals which are connected with bus system. t pr t pf t rpw t rpw t tpw 2.0 v 0.8 v 2.0 v 0.8 v 2.4 v 0.4 v 2.4 v 0.4 v f l f l t tpw t fd t trd transmit data slot receive data slot ltd htd lrd hrd (closest terminal) note 1 t ph (farthest terminal) note 2 htd/ltd htd/ltd note 1 indicates the terminal that is connected closest from the dsu. the signal from this terminal reaches the dsu the fastest. note 2 indicates the terminal that is connected farthest from the dsu. the signal from this terminal reaches the dsu the slowest. figure 5.1 timing at t ref. pt. interface
electrical characteristics - 19 - t rf t rdl t rdr t rr t rf t rdh t rr t rdf 2.0v 0 v 0.8 v 2.0 v 0.8 v lrd (o) hrd (o) receive signal (i) (li1 - li2) figure 5.2 receive timing r e t e m a r a pl o b m y sn o i t i d n o c. n i m. p y t. x a ms t i n u e m i t y a l e d t r d r 0 0 7s n t l d r 0 0 2s n t h d r 0 0 7s n t f d r 0 0 7s n e m i t e s i rt r r 1 e t o n 0 3s n e m i t l l a ft f r 2 e t o n 0 3s n t reference point receive characteristic (te mode) (v dd = 5.0 5% v, t op = -20 ~ 70 c, c l = 50 pf) note 1 with respect to hrd, lrd pins (odsel = h ) note 2 with respect to hrd, lrd pins note 3 figure 5.2 shows the timing when rdp = h . when rdp = l , the output signal polarity from hrd and lrd pins are inverted.
- 20 - electrical characteristics t sw 2.4 v 0.4 v 2.4 v 0.4 v 1.35 v 0.15 v -0.15 v -1.35 v t srh t srl t sw t sr t sf t sr t sf t sdz t sfh t sfh t sfl t sfl t srl t srh t gap transmit signal (o) (loi - lo2) ltd (i) htd (i) figure 5.3 transmit timing r e t e m a r pa ol b m sy on i t i d n co n. mi typ. max. ts i n u d o i r e p e s l u p d t l , d ht w t s 4.95 5.45 s p a g e s l u p d t l , d ht p a t g 260 ns e m i t e s i r d t l , d ht r t s e m i t l l a f d t l , d ht f t s 30 ns l a n g i s t i m s n a r t e m i t y a l e d t l r s 1 e t o n 490 ns t h r s 1 e t o n 1010 ns t h f s 1 e t o n 165 ns t l f s 1 e t o n 685 ns e m i t y a l e d s s o r c o r ze z d t s 1 e t o n 0 260 ns 1010 ns t reference point transmit characteristic (te mode) (v dd = 5.0 5% v, t op = -20 ~ 70 c, c l = 50 pf) note 1 measuring with r l voltage drop as shown in figure 5.4 note 2 figure 5.3 shows the timing when tdp = h. when tdp = l, the output signal polarity from hrd and lrd pins are inverted.
electrical characteristics - 21 - YTD428 htd ltd lo1 100 ? 200 ? r l r o lo2 transmit signal figure 5.4 transmit block test circuit driver, receiver i/o impedance s r e t e m a r a pl o b m y sn o i t i d n o c. n i m. p y t. x a ms t i n u e c n a d e p m i t u p n i r e v i e c e rz i l 2 i l - 1 i l0 5k ? e c n a d e p m i t u p u o r e v i r dz 1 o l ) 1 e t o n ( 2 o l - 1 o l0 5k ? e c n a d e p m i t u p u o r e v i r dz 0 o l ) 2 e t o n ( 2 o l - 1 o l5 1 ? note 1 when no pulse is output. note 2 when pulse is output.
- 22 - pin descriptions 6. pin descriptions
reference circuit - 23 - reference circuit the reference circuit using YTD428 is shown as bellow. clk1536 powmon reset tdp rdp odsel tsmpsel tsmpaut multi ntsel local lpsel exid clksel li1 lict cx2 li2 cx1 lo1 lo2 rx hrd lrd htd ltd rxu1 sgr rxu2 ruc sga rxs sgb sgbp sxa vrb vrt rev loop2a lpsw clk192k clk4k clk256k clk200 clk400 test0,2-9,21,22 test1,16-19 test10,11,24 test12 - 15 test20 test23, 25-27 test28 atei ateo d av ss 1 av dd 1 a1 av ss 2 av dd 2 a2 dv dd dv ss d a1 a1 a1 a1 a1 8(1%) 8(1%) 2sk2315 2sk2315 nl322522t-3r3j tdk 0.01 (10%) 560(1%) 560(1%) 1.8k(1%) 1.8k(1%) 15(1w) vrya15 1 /160v 15(1w) 1 1 kp4n12 fg fg trtepc9.8-0319c tdk 4 3 2 1 7 8 5 6 2sj278 2sj278 kp15n14 kp15n14 l2 l1 udp1 udm1 udm0 udp0 line activation circuit a2 fg rb ra ta tb 1s953 12 r(1%) r(1%) 8.2k 8.2k 0.1 1u 1u 1u 10k 10k 10k 10k 10k 10k 10k 10k 10k 11 5 3 a2 22 0.1 33k varistor 6 hrd lrd htd ltd i.430 ttl interface ytd418 or ytd423 clk1536 reset d line activation circuit line activation circuit 0.33 (10%) 0.0047 (10%) 0.0022 (10%) 0.015 (10%) 0.15 (10%) 0.1 0.1 0.1 YTD428 10k 1m 100 100

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